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ge ne ra l de sc ript ion the max349/max350 are 8-channel and dual 4-channel serially controlled multiplexers (muxes). these mux es conduct equally well in either direction. on-resist ance (100 max) is matched between switches to 16 max and is flat (10 max) over the specified signal range. these cmos devices can operate continuously with dual power supplies ranging from 2.7v to 8v or a sin- gle supply between +2.7v and +16v. each mux can handle rail-to-rail analog signals. the off-leakage current is only 0.1na at +25c or 5na at +85c. upon power-up, all switches are off and the interna l shift registers are reset to zero. the serial interface is compatible with spi?/qspi? and microwire?. functioning as a shift register, it allows data (at din) to be clocked in synchronously with the rising edge of clock (sclk). the shift reg isters output (dout) enables several max349s or max350s to be daisy chained. all digital inputs have 0.8v or 2.4v logic threshol ds, ensuring both ttl and cmos-logic compatibility when using 5v supplies or a single +5v supply. ________________________applic a t ions serial data-acquisition industrial and process- systems control systems avionics ate equipment audio signal routing networking ____________________________fe a t ure s ? spi/qspi, microwire-compatible serialinterface ? 8 separately controlled spst switches ? single 8-to-1 mux (max349)dual 4-to-1 mux (max350) ? 100 signal paths with 5v supplies ? rail-to-rail ? signal handling ? asynchronous reset input ? 2.7v to 8v dual supplies+2.7v to +16v single supply ? >2kv esd protection per method 3015.7 ? ttl/cmos-compatible inputs (with +5v or 5vsupplies) m ax 3 4 9 /m ax 3 5 0 se ria lly cont rolle d, low -volt a ge , 8 -cha nne l/dua l 4 -cha nne l m ult iple x e rs ________________________________________________________________ maxim integrated products 1 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 cs reset dout v- gnd din v+ sclk top view n.c. no7 no6 no5 no2 no1 no0 com 10 9 no4 no3 dip/so max349 logic 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 cs reset dout v- gnd din v+ sclk comb no0b no1b no2b no2a no1a no0a coma 10 9 no3b no3a dip/so max350 logic n.c. = not internally connected pin configura t ions/func t iona l dia gra m s 19-0451; rev 1; 10/98 part max349 cpn max349cwn max349cap 0c to +70c 0c to +70c 0c to +70c temp. range pin-package 18 plastic dip 18 wide so 20 ssop orde ring i nform a t ion ordering information continued at end of data sheet. *contact factory for dice specifications. max349c/d 0c to +70c dice* pin configurations continued at end of data sheet. spi and qspi are trademarks of motorola, inc. micr owire is a trademark of national semiconductor corp. rail-to-rail is a registered trademark of nippon mo torola, ltd. for free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800. for small orders, phone 1-800-835-8769. downloaded from: http:///
m ax 3 4 9 /m ax 3 5 0 se ria lly cont rolle d, low -volt a ge , 8 -cha nne l/dua l 4 -cha nne l m ult iple x e rs 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristicsdual supplies (v+ = +4.5v to +5.5v, v- = -4.5v to -5.5v, t a = t min to t max , unless otherwise noted. typical values are at t a = +25c.) stresses beyond those listed under absolute maximu m ratings may cause permanent damage to the device . these are stress ratings only, and functional operation of the device at these or any other condi tions beyond those indicated in the operational sec tions of the specifications is not implied. exposur e to absolute maximum rating conditions for extended per iods may affect device reliability. voltages referenced to gnd v+ ................................................. ..........................-0.3v, +17v v- ................................................. ...........................-17v, +0.3v v+ to v-........................................... ........................-0.3v, +17v sclk, cs , din, dout, reset .................-0.3v to (v+ + 0.3v) no, com ............................................ .....(v- - 2v) to (v+ + 2v) continuous current into any terminal............... ...............30ma peak current, no or com (pulsed at 1ms, 10% duty cycle).................... .............100ma continuous power dissipation (t a = +70c) 18-pin plastic dip (derate 11.11mw/c above +70c) ..889mw 18-pin so (derate 9.52mw/c above +70c)........... ....762mw 20-pin ssop (derate 8.00mw/c above +70c) ......... .640mw 18-pin cerdip (derate 10.53mw/c above +70c).....8 42mw operating temperature ranges max349c_ _, max350c_ _ ............................. ....0c to +70c max349e_ _, max350e_ _ ............................. ..-40c to +85c max349m_ _, max350m_ _ ...........................-5 5c to +125c storage temperature range .......................... ...-65c to +150c lead temperature (soldering, 10sec) ................ .............+300c conditions units min typ max (note 1) symbol parameter 60 100 v v- v+ v com , v no analog signal range v+ = 5v, v- = -5v, v com = 3v, i no = 1ma 125 r on com-no on-resistance c, e, m t a = +25c c, e, m t a = +25c 16 c, e, m v+ = 5v, v- = -5v, v com = 3v, i no = 1ma 20 ? r on com-no on-resistance match between channels (note 2) t a = +25c 10 c, e, m v+ = 5v, v- = -5v, i no = 1ma, v com = -3v, 0v, 3v 15 r flat(on) com-no on-resistance flatness (note 2) t a = +25c -0.1 0.002 0.1 analog switch c, e -5 5 v+ = 5.5v, v- = -5.5v, v com = -4.5v, v no = 4.5v m -10 10 t a = +25c -0.1 0.002 0.1 c, e -5 5 no off-leakage current (note 3) i no(off) v+ = 5.5v, v- = -5.5v, v com = 4.5v, v no = -4.5v m -10 10 na t a = +25c -0.1 0.002 0.1 c, e -10 10 m -100 100 t a = +25c -0.1 0.002 0.1 c, e -5 5 v+ = 5.5v, v- = -5.5v, v com = 4.5v, v no = 4.5v m -50 50 t a = +25c -0.2 0.002 0.2 c, e -10 10 m -100 100 t a = +25c -0.2 0.002 0.2 c, e -5 5 com off-leakage current (note 3) i com(off) v+ = 5.5v, v- = -5.5v, v com = -4.5v, v no = 4.5v m -50 50 na max349 max349 max350 max350 downloaded from: http:///
m ax 3 4 9 /m ax 3 5 0 se ria lly cont rolle d, low -volt a ge , 8 -cha nne l/dua l 4 -cha nne l m ult iple x e rs _______________________________________________________________________________________ 3 electrical characteristicsdual supplies (continued) (v+ = +4.5v to +5.5v, v- = -4.5v to -5.5v, t a = t min to t max , unless otherwise noted. typical values are at t a = +25c.) v 2.4 c, e, m v ih din, sclk, cs, reset input voltage logic threshold high max350 na -50 50 m v+ = 5.5v, v- = -5.5v, v com = v no = 4.5v com on-leakage current (note 3) i com(on) -5 5 c, e max349 -0.2 0.02 0.2 t a = +25c -100 100 m -10 10 c, e dout output voltage logic low v dout v i dout = -1.6ma 0 0.4 c, e, m mv 100 c, e, m dout output voltage logic high v dout sclk hyst v i dout = 0.8ma sclk input hysteresis 2.8 v+ c, e, m a -1 0.03 1 c, e, m v din , v sclk , v cs = 0.8v or 2.4v i ih, i il din, sclk, cs, reset input current logic high or low v 0.8 c, e, m v il din, sclk, cs , reset input voltage logic threshold low -0.2 0.001 0.2 t a = +25c turn-on time t on 400 ns from rising edge of cs c, e, m 200 275 t a = +25c -2 2 30 c, e, m c, e, m r l = 50 , c l = 15pf, v no = 1v rms , f = 100khz off-isolation v iso db pc pf pf charge injection (note 4) no off-capacitance com off-capacitance v cte c no(off) c com(off) v com = gnd, f = 1mhz c l = 1nf, v no = 0v, r s = 0 break-before-make delay t bbm 2 ns v no = gnd, f = 1mhz t a = +25c 2 t a = +25c 11 0 from rising edge of cs t a = +25c 54 0 t a = +25c parameter symbol min typ max (note 1) units v+ supply current i+ 72 0 a v- supply current i- -1 0.1 1 a turn-off time t off 300 ns from rising edge of cs c, e, m 90 150 t a = +25c din = cs = sclk = 0v or v+, reset = 0v or v+ din = cs = sclk = 0v or v+, reset = 0v or v+ channel-to-channel crosstalk v ct db < -90 r l = 50 , c l = 15pf, v no = 1v rms , f = 100khz t a = +25c switch on-capacitance c (on) > 90 c, e, m t a = +25c pf power-supply range v+, v- 3 8 v t a = +25c 8 conditions v com = v no = gnd, f = 1mhz t a = +25c t a = +25c digital i/o switch dynamic characteristics power supply downloaded from: http:///
m ax 3 4 9 /m ax 3 5 0 se ria lly cont rolle d, low -volt a ge , 8 -cha nne l/dua l 4 -cha nne l m ult iple x e rs 4 _______________________________________________________________________________________ sclk frequency f sclk reset minimum pulse width t rw 70 ns t a = +25c fall time of dout (note 4) t df 100 ns 20% of v+ to 70% of v+, c l = 10pf c, e, m allowable fall time at din, sclk (note 4) t scf 2 s 20% of v+ to 70% of v+, c l = 10pf c, e, m allowable rise time at din, sclk (note 4) t scr 2 s 20% of v+ to 70% of v+, c l = 10pf c, e, m rise time of dout (note 4) t dr 100 ns 20% of v+ to 70% of v+, c l = 10pf c, e, m din data valid after falling sclk (note 4) t do 400 ns data hold time minimum data setup time t ds 17 100 ns t dh 0 -17 85 50% of sclk to 10% of dout, c l = 10pf sclk low time ns t cl c, e, m 190 ns t a = +25c c, e, m c, e, m parameter symbol min typ max (note 1) units c, e, m sclk high time cs lag time t csh2 240 ns t ch 190 cs lead time cycle time ns t ch +t cl 480 t css 240 ns c, e, m 0 2.1 ns mhz c, e, m c, e, m c, e, m c, e, m conditions serial digital interface timing characteristicsdual supplies (figure 1) (v+ = +4.5v to +5.5v, v- = -4.5v to -5.5v, t a = t min to t max , unless otherwise noted. typical values are at t a = +25c.) note 1: the algebraic convention is used in this data sheet ; the most negative value is shown in the minimum c olumn. note 2: ? r on = r on(max) - r on(min) . on-resistance match between channels and on-resis tance flatness are guaranteed only with specified voltages. flatness is defined as the diff erence between the maximum and minimum value of on- resistance as measured over the specified analog signal range. note 3: leakage parameters are 100% tested at maximum rated hot temperature and guaranteed by correlation at r oom temp. note 4: guaranteed by design. note 5: leakage testing at single supply is guaranteed by t esting with dual supplies. note 6: see figure 6. off-isolation = 20log 10 v com /v no , v com = output. no = input to off switch. note 7: between any two switches. see figure 3. downloaded from: http:///
m ax 3 4 9 /m ax 3 5 0 se ria lly cont rolle d, low -volt a ge , 8 -cha nne l/dua l 4 -cha nne l m ult iple x e rs _______________________________________________________________________________________ 5 electrical characteristicssingle +5v supply (v+ = +4.5v to +5.5v, v- = 0v, t a = t min to t max , unless otherwise noted. typical values are at t a = +25c.) t a = +25c c, e, m 125 175 c, e, m v v- v+ v com , v no analog signal range t a = +25c -0.1 0.002 0.1 t a = +25c -0.2 0.002 0.2 c, e c, e conditions -10 10 -10 10 v+ = 5v, v com = 3.5v, i no = 1ma m -100 100 t a = +25c m -100 100 t a = +25c -0.2 0.002 0.2 max349 c, e -5 5 m 225 r on com-no on-resistance -50 50 -0.1 0.002 0.1 na v+ = 5.5v, v com = 0v, v no = 4.5v max350 i com(off) com off-leakage current (notes 4, 5) t a = +25c -0.2 0.01 0.2 c, e -10 10 m -100 100 t a = +25c -0.2 0.02 0.2 max349 c, e -5 5 m max349 -50 50 c, e -5 5 m -50 50 v+ = 5.5v, v com = v no = 4.5v na max350 v+ = 5.5v, v com = 4.5v, v no = 0v i com(on) com on-leakage current (notes 4, 5) max350 units min typ max (note 1) symbol parameter t a = +25c -0.1 0.002 0.1 c, e -5 5 m v+ = 5.5v, v com = 4.5v, v no = 0v -10 10 c, e, m 2.4 c, e, m 0.8 v il v ih din, sclk, cs, reset input voltage logic threshold low din, sclk, cs, reset input voltage logic threshold high v v c, e, m -1 0.03 1 c, e, m 2.8 v+ c, e, m 0 0.4 i dout = -1.6ma i dout = 0.8ma v din , v sclk , v cs = 0.8v or 2.4v v dout v dout i ih , i il dout output voltage logic low dout output voltage logic high din, sclk, cs, reset input current logic high or low v v a c, e, m 100 sclk hyst sclk input hysteresis mv t a = +25c 72 0 c, e, m 30 din = cs = sclk = 0v or v+, reset = 0v or v+ i+ v+ supply current a t a = +25c -0.1 0.002 0.1 c, e -5 5 m v+ = 5.5v, v com = 0v, v no = 4.5v na -10 10 i no(off) no off-leakage current (notes 4, 5) digital i/o analog switch power supply downloaded from: http:///
m ax 3 4 9 /m ax 3 5 0 se ria lly cont rolle d, low -volt a ge , 8 -cha nne l/dua l 4 -cha nne l m ult iple x e rs 6 _______________________________________________________________________________________ electrical characteristicssingle +5v supply (continued) (v+ = +4.5v to +5.5v, v- = 0v, t a = t min to t max , unless otherwise noted. typical values are at t a = +25c.) c l = 1nf, v no = 0v, r s = 0 v cte charge injection (note 4) pc db conditions t a = +25c t a = +25c 160 400 > 90 t a = +25c r l = 50 , c l = 15pf, v no = 1v rms , f = 100khz < -90 c, e, m from rising edge of cs ns db v iso v ct channel-to-channel crosstalk (note 7) off-isolation (note 6) r l = 50 , c l = 15pf, v no = 1v rms , f = 100khz 500 t on turn-on time t a = +25c 60 200 c, e, m from rising edge of cs ns 300 t off turn-off time units min typ max (note 1) symbol parameter t a = +25c 15 t a = +25c from rising edge of cs 11 0 ns t bbm break-before-make delay switch dynamic characteristics downloaded from: http:///
m ax 3 4 9 /m ax 3 5 0 se ria lly cont rolle d, low -volt a ge , 8 -cha nne l/dua l 4 -cha nne l m ult iple x e rs _______________________________________________________________________________________ 7 timing characteristicssingle +5v supply (figure 1) (v+ = +4.5v to +5.5v, v- = 0v, t a = t min to t max , unless otherwise noted. typical values are at t a = +25c.) serial digital interface serial digital interface rise time of dout (note 4) t dr 100 ns 20% of v+ to 70% of v+, c l = 10pf c, e, m allowable fall time at din, sclk (note 4) t scf 2 s 20% of v+ to 70% of v+, c l = 10pf c, e, m allowable rise time at din, sclk (note 4) t scr 2 s 20% of v+ to 70% of v+, c l = 10pf c, e, m din data valid after falling sclk (note 4) t do 400 ns data hold time (note 4) minimum data setup time (note 4) t ds 17 100 ns t dh -17 85 50% of sclk to 10% of dout, c l = 10pf sclk low time (note 4) ns t cl c, e, m 190 ns t a = +25c c, e, m c, e, m parameter symbol min typ max (note 1) units c, e, m sclk high time (note 4) cs lag time (note 4) t csh2 240 ns t ch 190 cs lead time (note 4) cycle time (note 4) sclk frequency f sclk ns 0 2.1 mhz t ch +t cl 480 t css 240 ns c, e, m ns c, e, m c, e, m c, e, m c, e, m conditions c, e, m 20% of v+ to 70% of v+, c l = 10pf ns 100 t df fall time of dout (note 4) note 1: the algebraic convention is used in this data sheet ; the most negative value is shown in the minimum c olumn. note 2: ? r on = r on(max) - r on(min) . on-resistance match between channels and on-resis tance flatness are guaranteed only with specified voltages. flatness is defined as the diff erence between the maximum and minimum value of on- resistance as measured over the specified analog signal range. note 3: leakage parameters are 100% tested at maximum rated hot temperature and guaranteed by correlation at r oom temp. note 4: guaranteed by design. note 5: leakage testing at single supply is guaranteed by t esting with dual supplies. note 6: see figure 6. off-isolation = 20log 10 v com /v no , v com = output. no = input to off switch. note 7: between any two switches. see figure 3. reset minimum pulse width t rw 70 ns t a = +25c downloaded from: http:///
m ax 3 4 9 /m ax 3 5 0 se ria lly cont rolle d, low -volt a ge , 8 -cha nne l/dua l 4 -cha nne l m ult iple x e rs 8 _______________________________________________________________________________________ v electrical characteristicssingle +3v supply (v+ = +3.0v to +3.6v, v- = 0v, t a = t min to t max , unless otherwise noted. typical values are at t a = +25c.) t a = +25c c, e, m 270 500 c, e, m c, e, m 100 v v- v+ v com , v no c, e 2.4 analog signal range t a = +25c -0.1 0.002 0.1 t a = +25c -0.2 0.002 0.2 c, e c, e conditions -10 10 -10 10 v+ = 3.0v, v com = 1.5v, i no = 1ma m -100 100 t a = +25c m -100 100 t a = +25c -0.2 0.002 0.2 c, e 0.8 max349 c, e -5 5 m 600 r on com-no on-resistance -50 50 -0.1 0.002 0.1 na v+ = 3.6v, v com = 0v, v no = 3v sclk hyst max350 i com(off) com off-leakage current (notes 4, 5) t a = +25c -0.2 0.01 0.2 c, e -10 10 m -100 100 t a = +25c sclk input hysteresis -0.2 0.02 0.2 max349 mv c, e -5 5 m v il v ih max349 -50 50 c, e -5 5 m -50 50 v+ = 3.6v, v com = v no = 3v na max350 v+ = 3.6v, v com = 3v, v no = 0v i com(on) com on-leakage current (notes 4, 5) din, sclk, cs , reset input voltage logic threshold low din, sclk, cs , reset input voltage logic threshold high v v c, e -1 0.03 1 c, e, m 2.8 v+ c, e, m max350 0 0.4 units min typ max (note 1) symbol parameter i dout = -1.6ma i dout = 0.1ma v din , v sclk , v cs = 0.8v or 2.4v v dout v dout i ih , i il dout output voltage logic low dout output voltage logic high din, sclk, cs , reset input current logic high or low v v a c, e, m 30 din = cs = sclk = 0v or v+, reset = 0v or 5v i+ v+ supply current a t a = +25c 62 0 digital i/o analog switch power supply downloaded from: http:///
m ax 3 4 9 /m ax 3 5 0 se ria lly cont rolle d, low -volt a ge , 8 -cha nne l/dua l 4 -cha nne l m ult iple x e rs _______________________________________________________________________________________ 9 m ax 3 4 9 /m ax 3 5 0 electrical characteristicssingle +3v supply (continued) (v+ = +3.0v to +3.6v, v- = 0v, t a = t min to t max , unless otherwise noted. typical values are at t a = +25c.) switch dynamic characteristics break-before-make delay (note 4) t bbm ns 11 0 from rising edge of cs t a = +25c 51 5 t a = +25c parameter symbol min typ max (note 1) units turn-off time (note 4) t off 400 ns from rising edge of cs c, e, m 120 300 t a = +25c turn-on time (note 4) t on 700 r l = 50 , c l = 15pf, v no = 1v rms , f = 100khz off-isolation (note 6) channel-to-channel crosstalk (note 7) v ct v iso db ns from rising edge of cs c, e, m < C90 r l = 50 , c l = 15pf, v no = 1v rms , f = 100khz t a = +25c > 90 275 600 t a = +25c t a = +25c conditions db pc charge injection (note 4) v cte c l = 1nf, v no = 0v, r s = 0 downloaded from: http:///
note 1: the algebraic convention is used in this data sheet ; the most negative value is shown in the minimum c olumn. note 2: ? r on = r on(max) - r on(min) . on-resistance match between channels and on-resis tance flatness are guaranteed only with specified voltages. flatness is defined as the diff erence between the maximum and minimum value of on- resistance as measured over the specified analog signal range. note 3: leakage parameters are 100% tested at maximum rated hot temperature and guaranteed by correlation at r oom temp. note 4: guaranteed by design. note 5: leakage testing at single supply is guaranteed by t esting with dual supplies. note 6: see figure 6. off-isolation = 20log 10 v com /v no , v com = output. no = input to off switch. note 7: between any two switches. see figure 3. m ax 3 4 9 /m ax 3 5 0 se ria lly cont rolle d, low -volt a ge , 8 -cha nne l/dua l 4 -cha nne l m ult iple x e rs 10 ______________________________________________________________________________________ timing characteristicssingle +3v supply (figure 1) (v+ = +3.0v to +3.6v, v- = 0v, t a = t min to t max , unless otherwise noted. typical values are at t a = +25c.) serial digital interface reset minimum pulse width (note 4) t rw 105 ns t a = +25c allowable fall time at din, sclk (note 4) t scf 2 s 20% of v+ to 70% of v+, c l = 10pf c, e, m fall time of dout (note 4) t df 100 ns 20% of v+ to 70% of v+, c l = 10pf c, e, m rise time of dout (note 4) t dr 100 ns 20% of v+ to 70% of v+, c l = 10pf c, e, m allowable rise time at din, sclk (note 4) t scr 2 s 20% of v+ to 70% of v+, c l = 10pf c, e, m din data valid after falling sclk (note 4) t do 400 ns data hold time (note 4) minimum data setup time (note 4) t ds 38 120 ns t dh -38 150 50% of sclk to 10% of dout, c l = 10pf sclk low time (note 4) ns t cl c, e, m 190 ns t a = +25c c, e, m c, e, m parameter symbol min typ max (note 1) units c, e, m sclk high time (note 4) cs lag time (note 4) t csh2 240 ns t ch 190 cs lead time (note 4) cycle time (note 4) sclk frequency f sclk ns 0 2.1 mhz t ch +t cl 480 t css 240 ns c, e, m ns c, e, m c, e, m c, e, m c, e, m conditions downloaded from: http:///
m ax 3 4 9 /m ax 3 5 0 se ria lly cont rolle d, low -volt a ge , 8 -cha nne l/dua l 4 -cha nne l m ult iple x e rs ______________________________________________________________________________________ 11 0 -5 -3 1 on-resistance vs. v com (dual supplies) 40 120 max349/350-toc1 v com (v) r on ( w ) -1 3 80 140 20 100 60 5 -4 0 -2 2 4 v = 5v v = 3v v = 2.5v 110 30 -5 -3 1 on-resistance vs. v com and tem perature (dual supplies) 50 90 max349/350-toc2 v com (v) r on ( w ) -1 3 70 100 40 80 60 5 -4 0 -2 2 4 v = 5.5v t a = +125c t a = +85c t a = +25c t a = -55c 0 04 on-resistance vs. v com (single supply) 100 300 max349/350-toc3 v com (v) r on ( w ) 8 200 400 350 50 250 150 21 0 1 2 6 v+ = 3v v+ = 12v v+ = 5v v+ = 2.5v v- = 0v v+ = 9v 180 02 on-resistance vs. v com and tem perature (single supply) 100 max349/350-toc4 v com (v) r on ( w ) 4 60 140 160 120 80 40 15 3 t a = +25c t a = -55c t a = +85c t a = +125c v+ = 5v v- = 0v 0.1 off-leakage vs. tem perature 1,000 max349/350-toc5 temperature (c) off-leakage (pa) 10 1 100 -50 125 25 -25 0 75 50 100 v = 5.5v 0.1 on-leakage vs. tem perature 1,000 10,000 max349/350-toc6 temperature (c) on-leakage (pa) 10 1 100 -50 125 25 -25 0 75 50 100 v = 5.5v __________________________________________typic a l o pe ra t ing cha ra c t e rist ic s (v+ = +5v, v- = -5v, gnd = 0v, t a = +25c, unless otherwise noted.) -5 -3 1 charge injection vs. v com -5 5 max349/350-toc7 v com (v) v cte (pc) -1 3 -4 4 -3 3 -2 2 -1 1 0 5 -4 0 -2 2 4 a: v+ = 5v, v- = -5v b: v+ = 5v, v- = 0v a b -5 -3 1 turn-on/turn-off tim es vs. v com 0 250 max349/350-toc8 v com (v) t on , t off (ns) -1 3 50 200 100 150 5 -4 0 -2 2 4 a = t on a: v+ = 5v, v- = 5v b: v+ = 5v, v- = 0v a = t off b = t off b = t on -50 04 data hold tim e vs. power-supply voltage -30 10 max349/350-toc9 supply voltage (v) data hold time (ns) 8 -10 30 40 50 20 -40 0 -20 26 downloaded from: http:///
m ax 3 4 9 /m ax 3 5 0 se ria lly cont rolle d, low -volt a ge , 8 -cha nne l/dua l 4 -cha nne l m ult iple x e rs 12 ______________________________________________________________________________________ 0 04 data setup tim e vs. positive supply voltage 20 60 max349/350-toc10 supply voltage (v) data setup time (ns) 8 40 80 90 100 70 10 50 30 26 100 0.001 -50 125 power-supply current vs. tem perature 10 1 max349/350-toc11 temperature (c) i+, i-, ( m a) 25 0.1 0.01 -25 0 75 50 100 v = 5.5v i+ i- 10 04 m inim um sclk pulse width vs. positive supply voltage 15 25 max349/350-toc12 supply voltage (v) sclk (ns) 8 20 30 35 26 0 -100 10k 100k 10m 1g frequency response -80 -20 max349/350 toc13 frequency (hz) loss (db) phase (degrees) 1m 100m -40 -60 20 -80 -100 -120 -60 0 -20 -40 phase off isolation insertion loss isolation of a bare socket v = 5v 50w in and out 0.01 10 100 1k 10k total harm onic distortion vs. frequency 0.1 max349/350-toc14 frequency (hz) tdh (% ) 1 10 100 v = 5v 600 w in and out typic a l ope ra t ing cha ra c t e rist ic s (c ont inue d) (v+ = +5v, v- = -5v, gnd = 0v, t a = +25c, unless otherwise noted.) downloaded from: http:///
m ax 3 4 9 /m ax 3 5 0 se ria lly cont rolle d, low -volt a ge , 8 -cha nne l/dua l 4 -cha nne l m ult iple x e rs ______________________________________________________________________________________ 13 pin de sc ript ion note: no and com pins are identical and interchangeable. either may be considered as an input or an output; signals pass equally well in either direction. sclk din dout com-out cs t do t dh t ds t css t ch t cl t csh2 t on , t off figure 1. timing diagram 1 serial clock digital input 2 positive analog supply voltage input 3 serial data digital input 5 common analog switch (mux output) 6C13 normally open analog switch inputs 0C7 common analog switch a (mux output) normally open analog switch a inputs 0C3 normally open analog switch b inputs 0C3 common analog switch b (mux output) 4 ground. connect to digital ground. (analog signals have no ground reference; they are limited to v+ and v-. ) 1 sclk 2 v+ 3 din 5 com 6C9, 11C14 no0Cno7 coma no0aCno3a no3bCno0b comb 4 gnd 15 negative analog supply voltage input. connect to gn d for single-supply operation. 16 serial data digital output. output high is v+. 17 reset input. connect to logic high (or v+) for norm al operation. drive low to set all switches off and set internal shift registers to 0. 18 chip-select digital input (figure 1) 17 v- 18 dout 19 reset 20 cs 14 no connect, not internally connected. 10, 15, 16 n.c. max349 ssop dip/so name function 1 2 3 5 6C9 10C13 14 4 1 2 3 5 6C9 11C14 15 4 15 16 17 18 17 18 19 20 10, 16 max350 ssop dip/so pin downloaded from: http:///
m ax 3 4 9 /m ax 3 5 0 se ria lly cont rolle d, low -volt a ge , 8 -cha nne l/dua l 4 -cha nne l m ult iple x e rs 14 ______________________________________________________________________________________ de t a ile d de sc ript ion ba sic ope ra t ion the max349/max350 are 8-channel and dual 4-chan- nel, serially controlled multiplexers (muxes). thes e muxes are unusual in that any, all, or none of the input channels can be directed to the output. all switche s are bidirectional, so inputs and outputs are inter- changeable. when multiple inputs are connected to a n output, they are also connected to one another, sep a- rated from each other only by the on-resistance of two switches. both parts require eight bits of serial d ata to set all eight switches. se ria l digit a l i nt e rfa c e the max349/max350 interface can be thought of as an 8-bit shift register controlled by cs (figure 2). while cs is low, input data appearing at din is clocked into the shift register synchronously with sclks rising edg e. the input is an 8-bit word, each bit controlling on e of the eight switches (tables 1 and 2). dout is the ou tput of the shift register, with data appearing synchron ously with sclks falling edge. data at dout is simply th e input data delayed by eight clock cycles. when shifting the input data, d7 is the first bit i n and out of the shift register. while shifting data, the switches remain in their previous configuration. when the ei ght bits of data have been shifted in, cs is driven high. this updates the new switch configuration and inhib its further data from entering the shift register. tran sitions at din and sclk have no effect when cs is high, and dout holds the first input bit (d7) at its output. more or fewer than eight clock cycles can be entere d during the cs low period. when this happens, the shift register contains only the last eight serial data b its, regardless of when they were entered. on the rising edge of cs , all switches are set to the corresponding states. the max349/max350 three-wire serial interface is compatible with spi, qspi, and microwire standards. if interfacing with a motorola processor serial int erface, set cpol = 0. the max349/max350 are considered to be slave devices (figures 2 and 3). at power-up, th e shift register contains all zeros, and all switches are off. the latch that drives the analog switch is updated on the rising edge of cs , regardless of sclks state. this meets all spi and qspi requirements. da isy-cha ining for a simple interface using several max349s and max350s, daisy-chain the shift registers as shown in figure 5. the cs pins of all devices are connected, and a stream of data is shifted through the max349s or max350s in series. when cs is brought high, all switches are updated simultaneously. additional shi ft registers may be included anywhere in series with t he max349/max350 data chain. note that the dout high level is v+, which may not be compatible with ttl/cmos devices if v+ differs from the logic suppl y for these other devices. addre ssa ble se ria l i nt e rfa c e when several serial devices are configured as slave s, addressable by the processor, din pins of each decode logic individually control cs of each slave device. when a slave is selected, its cs pin is driven low, data is shifted in, and cs is driven high to latch the data. typically, only one slave is addressed at a t ime. dout is not used. applic a t ions i nform a t ion 8 x 1 m ult iple x e r the max349 can be programmed normally, with only one channel selected for every eight clock pulses, or it can be programmed in a fast mode, where channel changing occurs on each clock pulse. in fast mode, select the channels by sending a sing le high pulse (corresponding to the selected channel) at di n, and a corresponding cs low pulse for every eight clock puls- es. as sclk clocks this through the register, each switch sequences one channel at a time, starting with chan nel 0. d7 d6 d5 d4 msb lsb d3 d2 d1 d0 data bits from previous data input dout power-up default: d7d0 = 0 d6 d5 d4 d3 d2 d1 d0 d7 dout din sclk switches updated data clocked in data clocked out cs d7 input data bits figure 2. 3-wire interface timing downloaded from: http:///
table 2. max350 serial-interface switch programming se ria lly cont rolle d, low -volt a ge , 8 -cha nne l/dua l 4 -cha nne l m ult iple x e rs m ax 3 4 9 /m ax 3 5 0 ______________________________________________________________________________________ 15 x = dont care. data bit d7 is first bit in; data bit d0 is last in. x 1 switch 0 open (off) x x x x 0 x x x max349 function x x x x 1 1 x data bits switch 0 closed to com x 0 0 1 0 1 1 1 all switches open, d7Cd0 = 0 switch 7 open (off) all switches closed to com, d7Cd0 = 1 all switches open, d7Cd0 = 0 x x 1 x 1 x 1 1 1 switch 6 open (off) switch 5 open (off) switch 6 closed to com switch 7 closed to com x 1 x 1 x 1 x 1 switch 4 open (off) switch 3 open (off) switch 4 closed to com switch 5 closed to com x 1 x 1 x 1 x 1 switch 2 open (off) switch 1 open (off) switch 2 closed to com switch 3 closed to com d7 0 x 1 x 0 x 1 x x x x x x x x x d6 0 0 x x 1 x 1 x x x x 0 x 1 x x x x x d4 x x 0 x x x x x 1 x x x x d5 0 0 x x 1 x 1 x x x x x x x x 0 x 1 x d2 0 0 x x 1 x 1 reset x x x x x x x x x x x x x x x d0 x x x x x x x x x x x 0 x x d1 x x 0 x x x x x 1 d3 x x x x x 1 x 1 switch 1 closed to com x table 1. max349 serial-interface switch programming x 1 switch no0a open (off) x x x x 0 x x x max350 function x x x x 1 1 x data bits switch no0a closed x 0 0 1 0 1 1 1 all switches open, d7Cd0 = 0 switch no0b open (off) all a switches closed to coma; all b switches closed to comb, d7Cd0 = 1 all switches open, d7Cd0 = 0 x x 1 x 1 x 1 1 1 switch no1b open (off) switch no2b open (off) switch no1b closed switch no0b closed x 1 x 1 x 1 x 1 switch no3b open (off) switch no3a open (off) switch no3b closed switch no2b closed x 1 x 1 x 1 x 1 switch no2a open (off) switch no1a open (off) switch no2a closed switch no3a closed d7 0 x 1 x 0 x 1 x x x x x x x x x d6 0 0 x x 1 x 1 x x x x 0 x 1 x x x x x d4 x x 0 x x x x x 1 x x x x d5 0 0 x x 1 x 1 x x x x x x x x 0 x 1 x d2 0 0 x x 1 x 1 reset x x x x x x x x x x x x x x x d0 x x x x x x x x x x x 0 x x d1 x x 0 x x x x x 1 d3 x x x x x 1 x 1 switch no1a closed x downloaded from: http:///
m ax 3 4 9 /m ax 3 5 0 se ria lly cont rolle d, low -volt a ge , 8 -cha nne l/dua l 4 -cha nne l m ult iple x e rs 16 ______________________________________________________________________________________ sclk din dout cs sk so si i/o microwire port max349 max350 the dout-si connection is not required for writing to the max349/max350, but may be used for data-echo purpos es. figure 3. connections for microwire dout din sclk cs miso mosi sck i/o spi port max349 max350 the dout-miso connection is not required for writin g to the max349/max350, but may be used for data-echo purpos es. cpol = 0, cpha = 0 figure 4. connections for spi and qspi sclk din cs max349 max350 sclk din cs max349 max350 sclk din cs max349 max350 dout dout dout sclk din cs to other serial devices figure 5. daisy-chained connection dua l, diffe re nt ia l 4 -cha nne l m ult iple x e r the max350 can be programmed normally, with only one differential channel selected for every eight c lock pulses, or it can be programmed in a fast mode, whe re channel changing occurs on each clock pulse. in fast mode, select the channels by sending two hi gh pulses, spaced four clock pulses apart (correspondi ng to the two selected channels) at din, and a corre- sponding cs low pulse for each of the first eight clock pulses. as sclk clocks this through the register, e ach switch sequences one differential channel at a time , starting with channel 0. repeat this process for su bse- quent channel sequencing after the first eight bits have been sent. for even faster channel sequencing, send only one din high pulse and one cs low pulse for every four clock pulses. re se t func t ion reset is the internal reset pin. it is usually connected to a logic signal or v+. drive reset low to open all switches and set the contents of the internal shift regis- ter to zero simultaneously. when reset is high, the part functions normally and dout is sourced from v+ . reset must not be driven beyond v+ or gnd. downloaded from: http:///
pow e r-supply conside ra t ions overview the max349/max350 construction is typical of most cmos analog switches. it has three supply pins: v+, v- and gnd. v+ and v- are used to drive the internal cmos switches, and they set the limits of the analo g voltage on any switch. reverse esd-protection diode s are internally connected between each analog signal pin and both v+ and v-. if any analog signal exceed s v+ or v-, one of these diodes will conduct. during normal operation, these (and other) reverse-biased esd dio des leak, forming the only current drawn from v+ or v-. virtually all the analog leakage current is through the esd diodes. although the esd diodes on a given sig- nal pin are identical, and therefore fairly well ba lanced, they are reverse biased differently. each is biased by either v+ or v- and the analog signal. this means t heir leakages vary as the signal varies. the difference in the two diode leakages to the v+ and v- pins constitute s the analog signal-path leakage current. all analog leak- age current flows to the supply terminals, not to t he other switch terminal. this is why both sides of a given switch can show leakage currents of either the same or opposite polarity. there is no connection between the analog signal paths and gnd. v+ and gnd power the internal logic and logic-level translators, and set both the input and output logi c lim- its. the logic-level translators convert the logic levels to switched v+ and v- signals to drive the analog sign al gates. this drive signal is the only connection bet ween the logic supplies (and signals) and the analog sup - plies. v+ and v- have esd-protection diodes to gnd. the logic-level inputs and output have esd protecti on to v+ and to gnd. the logic-level thresholds are cmos and ttl compati - ble when v+ is +5v. as v+ rises, the threshold incr eases slightly. therefore, when v+ reaches +12v, the thre shold is about 3.1v; above the ttl-guaranteed high-level mini- mum of 2.8v, but still compatible with cmos outputs . m ax 3 4 9 /m ax 3 5 0 se ria lly cont rolle d, low -volt a ge , 8 -cha nne l/dua l 4 -cha nne l m ult iple x e rs ______________________________________________________________________________________ 17 four clock pulses din sclk d4 sw4 d 0 sw 0 figure 7. differential multiplexer input control cs sclk din max349 max350 cs sclk din max349 max350 cs sclk din max349 max350 to other serial devices din sclk cs1 cs2 cs3 figure 6. addressable serial interface downloaded from: http:///
m ax 3 4 9 /m ax 3 5 0 se ria lly cont rolle d, low -volt a ge , 8 -cha nne l/dua l 4 -cha nne l m ult iple x e rs 18 ______________________________________________________________________________________ pin configura t ions/func t iona l dia gra m s (c ont inue d) 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 cs top view reset dout v- gnd din v+ sclk n.c. n.c. no7 no6 no2 no1 no0 com 12 11 9 10 no5 no4 n.c. no3 ssop max349 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 cs reset dout v- gnd din v+ sclk n.c. n.c. = not internally connected comb no0b no1b no2a no1a no0a coma 12 11 9 10 no2b no3b n.c. no3a ssop logic logic max350 bipolar supplies the max349/max350 operate with bipolar supplies from 3.0v and 8v. the v+ and v- supplies need not be symmetrical, but their sum cannot exceed the absolute maximum rating of 17v. do not connect the max349/max350 v+ to +3v and connect the logic-level pins to ttl logic-level signals. this exceeds the absolute maximum ratings and can damage the part and/or external circuits. single supply the max349/max350 operate from single supplies between +3v and +16v when v- is connected to gnd. all of the bipolar precautions must be observed. h igh-fre que nc y pe rform a nc e in 50 systems, signal response is reasonably flat up to 50mhz (see typical operating characteristics) . above 20mhz, the on response has several minor peaks that are highly layout dependent. the problem is not turning the switch on, but turning it off. the off-state switch acts like a capacitor and passes higher freq uen- cies with less attenuation. at 10mhz, off-isolation is about -45db in 50 systems, becoming worse (approx- imately 20db per decade) as frequency increases. higher circuit impedances also make off-isolation worse. adjacent channel attenuation is about 3db above that of a bare ic socket, and is entirely due to capacitive coupling. downloaded from: http:///
v- no0a din no2a 0. 120" (3. 05mm) 0. 100" (2. 54mm) no3a no3b no2b comb no0b no1b v+ sclk cs reset dout coma gnd no1a m ax 3 4 9 /m ax 3 5 0 se ria lly cont rolle d, low -volt a ge , 8 -cha nne l/dua l 4 -cha nne l m ult iple x e rs ______________________________________________________________________________________ 19 orde ring i nform a t ion (c ont inue d) * contact factory for dice specifications. ** contact factory for availability. _________________chip topogra phie s transistor count: 500 substrate connected to v+. 20 ssop -40c to +85c max350eap dice* 0c to +70c max350c/d 20 ssop -40c to +85c max349eap 18 cerdip** -55c to +125c max350mjn 18 wide so -40c to +85c max350ewn 18 plastic dip -40c to +85c max350epn 20 ssop 0c to +70c max350cap 18 wide so 18 plastic dip 0c to +70c 0c to +70c max350cwn max350 cpn 18 cerdip** -55c to +125c max349mjn 18 wide so 18 plastic dip pin-package temp. range -40c to +85c -40c to +85c max349ewn MAX349EPN part max349max350 v- no0 din no2 0. 120" (3. 05mm) 0. 100" (2. 54mm) no3 no4 no5 no7 no6 v+ sclk cs reset dout com gnd no1 downloaded from: http:///
m ax 3 4 9 /m ax 3 5 0 se ria lly cont rolle d, low -volt a ge , 8 -cha nne l/dua l 4 -cha nne l m ult iple x e rs maxim cannot assume responsibility for use of any c ircuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the cir cuitry and specifications without notice at any tim e. 20 ____________________m a x im i nt e gra t e d produc t s, 1 2 0 sa n ga brie l drive , sunnyva le , ca 9 4 0 8 6 4 0 8 -7 3 7 -7 6 0 0 ? 1998 maxim integrated products printed usa is a reg istered trademark of maxim integrated products. ___________________________________________________ _____pa c k a ge i nform a t ion ssop.eps soicw.eps downloaded from: http:///

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